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» Address Code Generation for Digital Signal Processors
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ITC
1998
IEEE
120views Hardware» more  ITC 1998»
15 years 3 months ago
Test generation in VLSI circuits for crosstalk noise
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
CORR
2011
Springer
211views Education» more  CORR 2011»
14 years 3 months ago
Programming Massively Parallel Architectures using MARTE: a Case Study
—Nowadays, several industrial applications are being ported to parallel architectures. These applications take advantage of the potential parallelism provided by multiple core pr...
Antonio Wendell De Oliveira Rodrigues, Fréd...
DAC
2006
ACM
15 years 5 months ago
Circuits for energy harvesting sensor signal processing
duce system weight and volume, increase operating lifetime, The recent explosion in capability of embedded and portable decrease maintenance costs, and open new frontiers for inele...
Rajeevan Amirtharajah, Justin Wenck, Jamie Collier...
ICASSP
2011
IEEE
14 years 3 months ago
Efficient iterative receiver for bit-Interleaved Coded Modulation according to the DVB-T2 standard
Bit-Interleaved Coded Modulation (BICM) offers a significant improvement in error correcting performance for coded modulations over fading channels compared to the previously exis...
Meng Li, Charbel Abdel Nour, Christophe Jég...
LCTRTS
2010
Springer
15 years 1 months ago
An efficient code update scheme for DSP applications in mobile embedded systems
DSP processors usually provide dedicated address generation units (AGUs) to assist address computation. By carefully allocating variables in the memory, DSP compilers take advanta...
Weijia Li, Youtao Zhang