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» Address Code Generation for Digital Signal Processors
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RTCSA
2006
IEEE
15 years 5 months ago
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors
To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constr...
Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu...
ICASSP
2011
IEEE
14 years 3 months ago
Joint algorithm-architecture optimization of CABAC to increase speed and reduce area cost
To address the increasing demand for higher resolution and frame rates, processing speed (i.e. performance) and area cost need to be considered in the development of next generati...
Vivienne Sze, Anantha P. Chandrakasan
SIGCOMM
2010
ACM
14 years 11 months ago
On the forwarding capability of mobile handhelds for video streaming over MANETs
Despite the importance of real-world experiments, nearly all ongoing research activities addressing video streaming over MANETs are based on simulation studies. Earlier research s...
Stein Kristiansen, Morten Lindeberg, Daniel Rodr&i...
CF
2010
ACM
15 years 4 months ago
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cach
As the number of transistors on a chip doubles with every technology generation, the number of on-chip cores also increases rapidly, making possible in a foreseeable future to des...
Pierre Michaud, Yiannakis Sazeides, André S...
LCTRTS
2000
Springer
15 years 3 months ago
Reordering Memory Bus Transactions for Reduced Power Consumption
Low energy consumption is becoming the primary design consideration for battery-operated and portable embedded systems, such as personal digital assistants, digital still and movi...
Bruce R. Childers, Tarun Nakra