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» Address Code Generation for Digital Signal Processors
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98
Voted
VLSID
2007
IEEE
154views VLSI» more  VLSID 2007»
15 years 12 months ago
Model Based Test Generation for Microprocessor Architecture Validation
Functional validation of microprocessors is growing in complexity in current and future microprocessors. Traditionally, the different components (or validation collaterals) used i...
Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Di...
RTCSA
2005
IEEE
15 years 5 months ago
Using UML 2.0 for System Level Design of Real Time SoC Platforms for Stream Processing
While enabling fast implementation and reconfiguration of stream applications, programmable stream processors expose issues of incompatibility and lack of adoption in existing st...
Yongxin Zhu, Zhenxin Sun, Alexander Maxiaguine, We...
ICCAD
1994
IEEE
116views Hardware» more  ICCAD 1994»
15 years 3 months ago
Design of heterogeneous ICs for mobile and personal communication systems
{ Mobile and personal communication systems form key market areas for the electronics industry of the nineties. Stringent requirements in terms of exibility, performance and power...
Gert Goossens, Ivo Bolsens, Bill Lin, Francky Catt...
99
Voted
ERLANG
2004
ACM
15 years 5 months ago
HiPE on AMD64
Erlang is a concurrent functional language designed for developing large-scale, distributed, fault-tolerant systems. The primary implementation of the language is the Erlang/OTP s...
Daniel Luna, Mikael Pettersson, Konstantinos F. Sa...
FPL
2008
Springer
113views Hardware» more  FPL 2008»
15 years 1 months ago
Mapping and scheduling with task clustering for heterogeneous computing systems
This paper presents a new approach for mapping task graphs to heterogeneous hardware/software computing systems using heuristic search techniques. Two techniques: (1) integration ...
Yuet Ming Lam, José Gabriel F. Coutinho, Wa...