233 search results - page 24 / 47 » Address Code Generation for Digital Signal Processors |
VLSID
2006
IEEE
15 years 5 months ago
2006
IEEE
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
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PLDI
2004
ACM
15 years 5 months ago
2004
ACM
It has long been known that a fixed ordering of optimization phases will not produce the best code for every application. One approach for addressing this phase ordering problem ...
ISCA
1995
IEEE
15 years 3 months ago
1995
IEEE
One can e ectively utilize predicated execution to improve branch handling in instruction-level parallel processors. Although the potential bene ts of predicated execution are hig...
ICS
2009
Tsinghua U.
15 years 6 months ago
2009
Tsinghua U.
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
CODES
2004
IEEE
15 years 3 months ago
2004
IEEE
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...