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» Address Code Generation for Digital Signal Processors
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114
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ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
15 years 5 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
85
Voted
KBSE
2005
IEEE
15 years 5 months ago
An analysis of rule coverage as a criterion in generating minimal test suites for grammar-based software
The term grammar-based software describes software whose input can be specified by a context-free grammar. This grammar may occur explicitly in the software, in the form of an in...
Mark Hennessy, James F. Power
ICASSP
2011
IEEE
14 years 3 months ago
A cochlear neuron based robust feature for speaker recognition
In this paper, a robust feature for text-independent speaker recognition is proposed, which simulate the response mode of cochlear neurons in processing acoustic signal. The featu...
Datao You, Tao Jiang, Jiqing Han, Tieran Zheng
89
Voted
ICASSP
2010
IEEE
14 years 11 months ago
Anti-forensics of JPEG compression
The widespread availability of photo editing software has made it easy to create visually convincing digital image forgeries. To address this problem, there has been much recent w...
Matthew C. Stamm, Steven K. Tjoa, W. Sabrina Lin, ...
108
Voted
ASPLOS
1998
ACM
15 years 3 months ago
Cache-Conscious Data Placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Brad Calder, Chandra Krintz, Simmi John, Todd M. A...