233 search results - page 28 / 47 » Address Code Generation for Digital Signal Processors |
109
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CASES
2006
ACM
15 years 3 months ago
2006
ACM
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
ISCAS
2006
IEEE
15 years 5 months ago
2006
IEEE
This paper describes an on-chip programmable bias current generator, intended for mixed signal chips requiring a wide ranging set of currents. The individual generators share a ma...
PLDI
2005
ACM
15 years 5 months ago
2005
ACM
Modulo scheduling is an effective code generation technique that exploits the parallelism in program loops by overlapping iterations. One drawback of this optimization is that reg...
126
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CASES
2005
ACM
15 years 1 months ago
2005
ACM
Code compression is a field where compression ratios between compiler-generated code and subsequent compressed code are highly dependent on decisions made at compile time. Most op...
ISLPED
2005
ACM
15 years 5 months ago
2005
ACM
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called Cluster of Active Disks (CAD), where the storag...