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» Address Code Generation for Digital Signal Processors
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CODES
2005
IEEE
15 years 5 months ago
Iterational retiming: maximize iteration-level parallelism for nested loops
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation ...
Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean ...
TVLSI
2010
14 years 6 months ago
Dynamic and Leakage Energy Minimization With Soft Real-Time Loop Scheduling and Voltage Assignment
With the shrinking of technology feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Traditional dynamic voltage scaling (DVS) fail...
Meikang Qiu, Laurence Tianruo Yang, Zili Shao, Edw...
CJ
2006
84views more  CJ 2006»
14 years 11 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
ISCAS
2005
IEEE
190views Hardware» more  ISCAS 2005»
15 years 5 months ago
A complete receiver solution for a chaotic direct-sequence spread spectrum communication system
— This paper is devoted to receiver design in a Chaotic Direct-Sequence Spread Spectrum (CD3S) digital communication system. The demodulation is achieved through chaos synchroniz...
M. B. Luca, S. Azou, G. Burel, A. Serbanescu
APCCAS
2006
IEEE
251views Hardware» more  APCCAS 2006»
15 years 5 months ago
Design of a Dynamic PCM Selector for Non-deterministic Environment
—The quality of transmission is very important in digital communication. However, in non-deterministic environment or different transmission message signal, bit error rate of PCM...
Liang-Bi Chen, Ing-Jer Huang, Yuan-Long Jeang