Sciweavers

233 search results - page 34 / 47
» Address Code Generation for Digital Signal Processors
Sort
View
APSEC
2006
IEEE
15 years 5 months ago
Testing of Timer Function Blocks in FBD
Testing for time-related behaviors of PLC software is important and should be performed carefully. We propose a structural testing technique on Function Block Diagram(FBD) network...
Eunkyoung Jee, Seungjae Jeon, Hojung Bang, Sung De...
CODES
2008
IEEE
15 years 6 months ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
SEMWEB
2001
Springer
15 years 4 months ago
Adding Multimedia to the Semantic Web: Building an MPEG-7 ontology
For the past two years the Moving Pictures Expert Group (MPEG), a working group of ISO/IEC, have been developing MPEG-7 [1], the "Multimedia Content Description Interface"...
Jane Hunter
ASPDAC
2005
ACM
146views Hardware» more  ASPDAC 2005»
15 years 1 months ago
High-level synthesis for DSP applications using heterogeneous functional units
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...
Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edw...
MTA
2006
115views more  MTA 2006»
14 years 11 months ago
Cache modeling and optimization for portable devices running MPEG-4 video decoder
Abstract There are increasing demands on portable communication devices to run multimedia applications. ISO (an International Organization for Standardization) standard MPEG-4 is a...
Abu Asaduzzaman, Imad Mahgoub