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» Address Code Generation for Digital Signal Processors
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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
14 years 12 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
MOBICOM
2012
ACM
13 years 2 months ago
Distinguishing users with capacitive touch communication
As we are surrounded by an ever-larger variety of post-PC devices, the traditional methods for identifying and authenticating users have become cumbersome and time-consuming. In t...
Tam Vu, Akash Baid, Simon Gao, Marco Gruteser, Ric...
WWW
2007
ACM
16 years 11 days ago
A high-performance interpretive approach to schema-directed parsing
XML delivers key advantages in interoperability due to its flexibility, expressiveness, and platform-neutrality. As XML has become a performance-critical aspect of the next genera...
Morris Matsa, Eric Perkins, Abraham Heifets, Marga...
KBSE
2007
IEEE
15 years 6 months ago
Improving evolutionary class testing in the presence of non-public methods
Automating the generation of object-oriented unit tests is a challenging task. This is mainly due to the complexity and peculiarities that the principles of object-orientation imp...
Stefan Wappler, Ina Schieferdecker
POPL
2004
ACM
16 years 5 hour ago
Parsing expression grammars: a recognition-based syntactic foundation
For decades we have been using Chomsky's generative system of grammars, particularly context-free grammars (CFGs) and regular expressions (REs), to express the syntax of prog...
Bryan Ford