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» Address Code Generation for Digital Signal Processors
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VLSISP
2008
100views more  VLSISP 2008»
15 years 1 months ago
Memory-constrained Block Processing for DSP Software Optimization
Digital signal processing (DSP) applications involve processing long streams of input data. It is important to take into account this form of processing when implementing embedded ...
Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattach...
132
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DSN
2007
IEEE
15 years 5 months ago
Augmenting Branch Predictor to Secure Program Execution
Although there are various ways to exploit software vulnerabilities for malicious attacks, the attacks always result in unexpected behavior in program execution, deviating from wh...
Yixin Shi, Gyungho Lee
118
Voted
BMCBI
2010
132views more  BMCBI 2010»
15 years 1 months ago
Data structures and compression algorithms for high-throughput sequencing technologies
Background: High-throughput sequencing (HTS) technologies play important roles in the life sciences by allowing the rapid parallel sequencing of very large numbers of relatively s...
Kenny Daily, Paul Rigor, Scott Christley, Xiaohui ...
ISCA
2009
IEEE
152views Hardware» more  ISCA 2009»
15 years 8 months ago
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken...
ISCA
2010
IEEE
219views Hardware» more  ISCA 2010»
15 years 6 months ago
Using hardware vulnerability factors to enhance AVF analysis
Fault tolerance is now a primary design constraint for all major microprocessors. One step in determining a processor’s compliance to its failure rate target is measuring the Ar...
Vilas Sridharan, David R. Kaeli