233 search results - page 44 / 47 » Address Code Generation for Digital Signal Processors |
CGO
2008
IEEE
15 years 4 months ago
2008
IEEE
Array inlining expands the concepts of object inlining to arrays. Groups of objects and arrays that reference each other are placed consecutively in memory so that their relative ...
85
Voted
EMSOFT
2009
Springer
15 years 4 months ago
2009
Springer
An important step in model-based embedded system design consists in mapping functional specifications and their tasks/operations onto execution architectures and their ressources...
84
Voted
ICS
2007
Tsinghua U.
15 years 3 months ago
2007
Tsinghua U.
Sensitivity Analysis (SA) is a novel compiler technique that complements, and integrates with, static automatic parallelization analysis for the cases when relevant program behavi...
VEE
2009
ACM
15 years 4 months ago
2009
ACM
r of high-level languages lies in their abstraction over hardware and software complexity, leading to greater security, better reliability, and lower development costs. However, o...
80
Voted
ICS
2009
Tsinghua U.
15 years 4 months ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...