233 search results - page 7 / 47 » Address Code Generation for Digital Signal Processors |
IPPS
2010
IEEE
14 years 9 months ago
2010
IEEE
Abstract--Loop tiling is an important compiler transformation used for enhancing data locality and exploiting coarsegrained parallelism. Tiled codes in which tile sizes are runtime...
FPL
2005
Springer
15 years 5 months ago
2005
Springer
As the logic capacity of FPGA increases, there has been a corresponding increase in the variety of FPGA building blocks. From a mere collection of the conventional logic blocks, F...
130
Voted
ASAP
1997
IEEE
15 years 3 months ago
1997
IEEE
Improvements in semiconductor integration density and the resulting problem of having to manage designs of increasing complexity is an old one, but still current. The new challeng...
115
Voted
LCTRTS
2005
Springer
15 years 5 months ago
2005
Springer
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...
IEEEPACT
2000
IEEE
15 years 3 months ago
2000
IEEE
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...