233 search results - page 9 / 47 » Address Code Generation for Digital Signal Processors |
107
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ICIP
2004
IEEE
16 years 1 months ago
2004
IEEE
We present a practical scheme for error-resilient digital video broadcasting, using the Wyner-Ziv coding paradigm. We apply the general framework of systematic lossy source-channe...
VLSISP
1998
14 years 11 months ago
1998
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
CODES
2007
IEEE
15 years 5 months ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
104
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ISCAS
1994
IEEE
15 years 3 months ago
1994
IEEE
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
ISLPED
2003
ACM
15 years 4 months ago
2003
ACM
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...