562 search results - page 70 / 113 » Address Code and Arithmetic Optimizations for Embedded Syste... |
164
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CODES
2005
IEEE
15 years 11 months ago
2005
IEEE
Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application...
175
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EMSOFT
2004
Springer
15 years 10 months ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
133
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CASES
2004
ACM
15 years 10 months ago
2004
ACM
Abstract— In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache ...
162
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ICASSP
2008
IEEE
15 years 12 months ago
2008
IEEE
We propose a low-delay low-complexity end-to-end video transmission system that integrates the latest scalable H.264 codec and the full-rate full-diversity quasi-orthogonal space-...
176
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ICCD
1999
IEEE
15 years 9 months ago
1999
IEEE
In this paper, we present a hierarchical evolutionary approach to hardware/software partitioning for real-time embedded systems. In contrast to most of previous approaches, we app...