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DAC
1999
ACM
16 years 4 months ago
Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting
We illustrate how technical contributions in the VLSI CAD partitioning literature can fail to provide one or more of: (i) reproducible results and descriptions, (ii) an enabling a...
Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Ken...
DAC
2005
ACM
16 years 4 months ago
Fine-grained application source code profiling for ASIP design
Current Application Specific Instruction set Processor (ASIP) design methodologies are mostly based on iterative architecture exploration that uses Architecture Description Langua...
Kingshuk Karuri, Mohammad Abdullah Al Faruque, Ste...
DAC
2006
ACM
16 years 4 months ago
Power-centric design of high-speed I/Os
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is const...
Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojan...
ICML
2006
IEEE
16 years 4 months ago
Two-dimensional solution path for support vector regression
Recently, a very appealing approach was proposed to compute the entire solution path for support vector classification (SVC) with very low extra computational cost. This approach ...
Gang Wang, Dit-Yan Yeung, Frederick H. Lochovsky
ICML
2004
IEEE
16 years 4 months ago
Solving cluster ensemble problems by bipartite graph partitioning
A critical problem in cluster ensemble research is how to combine multiple clusterings to yield a final superior clustering result. Leveraging advanced graph partitioning techniqu...
Xiaoli Zhang Fern, Carla E. Brodley