Sciweavers

2124 search results - page 341 / 425
» Aggregating time partitions
Sort
View
CODES
2003
IEEE
15 years 5 months ago
A codesigned on-chip logic minimizer
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
Roman L. Lysecky, Frank Vahid
CODES
2003
IEEE
15 years 5 months ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
DATE
2003
IEEE
124views Hardware» more  DATE 2003»
15 years 5 months ago
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration
– Floorplanning large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. This paper presents a global flo...
Wonjoon Choi, Kia Bazargan
GLVLSI
2003
IEEE
153views VLSI» more  GLVLSI 2003»
15 years 5 months ago
FORCE: a fast and easy-to-implement variable-ordering heuristic
The MINCE heuristic for variable-ordering [1] successfully reduces the size of BDDs and can accelerate SAT-solving. Applications to reachability analysis have also been successful...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
INFOCOM
2003
IEEE
15 years 5 months ago
Receiver-Driven Bandwidth Sharing for TCP
— Applications using TCP, such as web-browsers, ftp, and various P2P programs, dominate most of the Internet traffic today. In many cases the last-hop access links are bottlenec...
Puneet Mehra, Christophe De Vleeschouwer, Avideh Z...