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WADS
2005
Springer
95views Algorithms» more  WADS 2005»
15 years 3 months ago
Improved Combinatorial Group Testing for Real-World Problem Sizes
We study practically efficient methods for performing combinatorial group testing. We present efficient non-adaptive and two-stage combinatorial group testing algorithms, which i...
David Eppstein, Michael T. Goodrich, Daniel S. Hir...
ICCD
2003
IEEE
89views Hardware» more  ICCD 2003»
15 years 3 months ago
Power-Time Tradeoff in Test Scheduling for SoCs
We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use t...
Mehrdad Nourani, James Chin
DATE
2010
IEEE
120views Hardware» more  DATE 2010»
15 years 3 months ago
Memory testing with a RISC microcontroller
—Many systems are based on embedded microcontrollers. Applications demand for production and Power-On testing, including memory testing. Because low-end microcontrollers may not ...
A. J. van de Goor, Georgi Gaydadjiev, Said Hamdiou...
96
Voted
ISCAS
2011
IEEE
248views Hardware» more  ISCAS 2011»
14 years 1 months ago
SNR measurement based on linearity test for ADC BIST
—Linearity and spectral performance test contributes most cost of ADC test. This paper presents a new method for testing an ADC’s SNR from its linearity test data. The method d...
Jingbo Duan, Degang Chen
ATS
2009
IEEE
99views Hardware» more  ATS 2009»
15 years 5 months ago
Test Generation for Designs with On-Chip Clock Generators
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
Xijiang Lin, Mark Kassab