We study practically efficient methods for performing combinatorial group testing. We present efficient non-adaptive and two-stage combinatorial group testing algorithms, which i...
David Eppstein, Michael T. Goodrich, Daniel S. Hir...
We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use t...
—Many systems are based on embedded microcontrollers. Applications demand for production and Power-On testing, including memory testing. Because low-end microcontrollers may not ...
A. J. van de Goor, Georgi Gaydadjiev, Said Hamdiou...
—Linearity and spectral performance test contributes most cost of ADC test. This paper presents a new method for testing an ADC’s SNR from its linearity test data. The method d...
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...