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LICS
2006
IEEE
16 years 12 days ago
Temporal Logics and Model Checking for Fairly Correct Systems
We motivate and study a generic relaxation of correctness of reactive and concurrent systems with respect to a temporal specification. We define a system to be fairly correct if...
Daniele Varacca, Hagen Völzer
139
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APSEC
2005
IEEE
16 years 18 hour ago
A Lightweight Integration of Theorem Proving and Model Checking for System Verification
Weiqiang Kong, Takahiro Seino, Kokichi Futatsugi, ...
114
Voted
DATE
2005
IEEE
98views Hardware» more  DATE 2005»
16 years 12 hour ago
Space-Efficient Bounded Model Checking
Jacob Katz, Ziyad Hanna, Nachum Dershowitz
LICS
2005
IEEE
15 years 12 months ago
Model-Checking Hierarchical Structures
Hierarchical graph definitions allow a modular description of graphs using modules for the specification of repeated substructures. Beside this modularity, hierarchical graph de...
Markus Lohrey