6939 search results - page 718 / 1388 » Algorithm Engineering for Parallel Computation |
176
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EUROPAR
2009
Springer
16 years 1 months ago
2009
Springer
Moore’s Law suggests that the number of processing cores on a single chip increases exponentially. The future performance increases will be mainly extracted from thread-level par...
189
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JSSPP
2009
Springer
16 years 1 months ago
2009
Springer
The number of applications with many parallel cooperating processes is steadily increasing, and developing efficient runtimes for their execution is an important task. Several fram...
212
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ICPADS
2002
IEEE
16 years 7 days ago
2002
IEEE
Wormhole routing is most common in parallel architectures in which messages are sent in small fragments called flits. It is a lightweight and efficient method of routing message...
219
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IPPS
2002
IEEE
16 years 6 days ago
2002
IEEE
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is do...
200
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ICS
1999
Tsinghua U.
15 years 11 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...