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110
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DAC
2001
ACM
16 years 3 months ago
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
Jason Cong, Michail Romesis
126
Voted
WWW
2003
ACM
16 years 3 months ago
A Caching Mechanism for Improving Internet based Mobile Ad Hoc Networks Performance
Internet based mobile ad hoc networks (IMANETs) have several limitations to fulfill users' demands to access various kinds of information such as limited accessibility to the...
Sunho Lim, Seung-Taek Park, Wang-Chien Lee, Guohon...
ICCD
2001
IEEE
154views Hardware» more  ICCD 2001»
15 years 11 months ago
Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model
As the operating frequency increases to Giga Hertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a line, it is necessary to consider the...
Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
ICCAD
2005
IEEE
107views Hardware» more  ICCAD 2005»
15 years 11 months ago
Projection-based performance modeling for inter/intra-die variations
Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations....
Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J...
ISCA
2009
IEEE
138views Hardware» more  ISCA 2009»
15 years 9 months ago
Achieving predictable performance through better memory controller placement in many-core CMPs
In the near term, Moore’s law will continue to provide an increasing number of transistors and therefore an increasing number of on-chip cores. Limited pin bandwidth prevents th...
Dennis Abts, Natalie D. Enright Jerger, John Kim, ...