Sciweavers

23590 search results - page 4536 / 4718
» Algorithm Performance Contest
Sort
View
MICRO
2008
IEEE
72views Hardware» more  MICRO 2008»
15 years 11 months ago
Low-power, high-performance analog neural branch prediction
Shrinking transistor sizes and a trend toward low-power processors have caused increased leakage, high per-device variation and a larger number of hard and soft errors. Maintainin...
Renée St. Amant, Daniel A. Jiménez, ...
3DIM
2007
IEEE
15 years 11 months ago
Robust 2D-3D alignment based on geometrical consistency
This paper presents a new registration algorithm of a 2D image and a 3D geometrical model, which is robust for initial registration errors, for reconstructing a realistic 3D model...
Kenji Hara, Yuuki Kabashima, Yumi Iwashita, Ryo Ku...
CCGRID
2007
IEEE
15 years 11 months ago
Revisit of View-Oriented Parallel Programming
Traditional parallel programming styles have many problems which hinder the development of parallel applications. The message passing style can be too complex for many programmers...
Z. Huang, W. Chen
CODES
2007
IEEE
15 years 11 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
189
Voted
ECRTS
2007
IEEE
15 years 11 months ago
Cache-Aware Timing Analysis of Streaming Applications
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...
Samarjit Chakraborty, Tulika Mitra, Abhik Roychoud...
« Prev « First page 4536 / 4718 Last » Next »