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» Algorithm Transformation for FPGA Implementation
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DATE
2007
IEEE
112views Hardware» more  DATE 2007»
15 years 8 months ago
Compact hardware design of Whirlpool hashing core
Weaknesses have recently been found in the widely used cryptographic hash functions SHA-1 and MD5. A potential alternative for these algorithms is the Whirlpool hash function, whi...
Timo Alho, Panu Hämäläinen, Marko H...
DAC
1997
ACM
15 years 6 months ago
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets
The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the...
Marleen Adé, Rudy Lauwereins, J. A. Peperst...
ERSA
2008
103views Hardware» more  ERSA 2008»
15 years 3 months ago
A Hardware Accelerator for k-th Nearest Neighbor Thinning
This paper presents an accelerator for k-th nearest neighbor thinning, a run time intensive algorithmic kernel used in recent multi-objective optimizers. We discuss the thinning al...
Tobias Schumacher, Robert Meiche, Paul Kaufmann, E...
WOSP
2005
ACM
15 years 7 months ago
From UML to LQN by XML algebra-based model transformations
The change of focus from code to models promoted by OMG's Model Driven Development raises the need for verification of nonfunctional characteristics of UML models, such as pe...
Gordon Ping Gu, Dorina C. Petriu
ICFP
2010
ACM
15 years 3 months ago
Bidirectionalizing graph transformations
Bidirectional transformations provide a novel mechanism for synchronizing and maintaining the consistency of information between input and output. Despite many promising results o...
Soichiro Hidaka, Zhenjiang Hu, Kazuhiro Inaba, Hir...