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» Algorithm Transformation for FPGA Implementation
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TCSV
2002
148views more  TCSV 2002»
15 years 1 months ago
A full-featured, error-resilient, scalable wavelet video codec based on the set partitioning in hierarchical trees (SPIHT) algor
Compressed video bitstreams require protection from channel errors in a wireless channel. The threedimensional (3-D) SPIHT coder has proved its efficiency and its real-time capabi...
Sungdae Cho, William A. Pearlman
IPPS
2008
IEEE
15 years 8 months ago
Energy efficient packet classification hardware accelerator
Packet classification is an important function in a router’s line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classifi...
Alan Kennedy, Xiaojun Wang, Bin Liu
CHES
2007
Springer
154views Cryptology» more  CHES 2007»
15 years 8 months ago
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
Abstract. This paper presents a design-space exploration of the Galois/Counter Mode (GCM) algorithm with Advanced Encryption Standard (AES) as underlying block cipher for high thro...
Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert ...
DATE
2005
IEEE
180views Hardware» more  DATE 2005»
15 years 7 months ago
A Coprocessor for Accelerating Visual Information Processing
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of mic...
Walter Stechele, L. Alvado Cárcel, Stephan ...
FCCM
2000
IEEE
148views VLSI» more  FCCM 2000»
15 years 6 months ago
An Adaptive Cryptographic Engine for IPSec Architectures
Architectures that implement the Internet Protocol Security (IPSec) standard have to meet the enormous computing demands of cryptographic algorithms. In addition, IPSec architectu...
Andreas Dandalis, Viktor K. Prasanna, José ...