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» Algorithm Transformation for FPGA Implementation
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95
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IESS
2007
Springer
92views Hardware» more  IESS 2007»
15 years 3 months ago
An Interactive Model Re-Coder for Efficient SoC Specification
To overcome the complexity in System-on-Chip (SoC) design, researchers have developed sophisticated design flows that significantly reduce the development time through automation...
Pramod Chandraiah, Rainer Dömer
ACSAC
2006
IEEE
15 years 3 months ago
PolyUnpack: Automating the Hidden-Code Extraction of Unpack-Executing Malware
Modern malware often hide the malicious portion of their program code by making it appear as data at compiletime and transforming it back into executable code at runtime. This obf...
Paul Royal, Mitch Halpin, David Dagon, Robert Edmo...
ISPDC
2006
IEEE
15 years 3 months ago
How to Achieve High Throughput with Dynamic Tree-Structured Coterie
Data replication permits a better network bandwidth utilization and minimizes the effect of latency in large-scale systems such as computing grids. However, the cost of maintainin...
Ivan Frain, Abdelaziz Mzoughi, Jean Paul Bahsoun
69
Voted
MMM
2006
Springer
128views Multimedia» more  MMM 2006»
15 years 3 months ago
An improved distortion model for rate control of DCT-based video coding
This paper presents a rate control algorithm for the dominant discrete cosine transform (DCT) -based video coding. It is developed based on a more accurate rate-distortion (RD) mo...
Jun Xie, Liang-Tien Chia, Bu-Sung Lee
106
Voted
QEST
2006
IEEE
15 years 3 months ago
Compositional Performability Evaluation for STATEMATE
Abstract— This paper reports on our efforts to link an industrial state-of-the-art modelling tool to academic state-of-the-art analysis algorithms. In a nutshell, we enable timed...
Eckard Böde, Marc Herbstritt, Holger Hermanns...