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» Algorithm Transformation for FPGA Implementation
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FCCM
2004
IEEE
91views VLSI» more  FCCM 2004»
15 years 1 months ago
An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding
We propose a parallel architecture for implementing the interpolation step in the Koetter-Vardy soft-decision ReedSolomon decoding algorithm. The key feature is the embedding of b...
Warren J. Gross, Frank R. Kschischang, P. Glenn Gu...
ICASSP
2011
IEEE
14 years 1 months ago
A FPGA architecture for real-time processing of variable-length FFTS
A new FFT architecture for real-time implementation of large FFTs is presented. The architecture supports both, highthroughput and variable-length processing capabilities. The imp...
Stefan Langemeyer, Peter Pirsch, Holger Blume
CDC
2010
IEEE
136views Control Systems» more  CDC 2010»
14 years 4 months ago
Multi-resolution path planning: Theoretical analysis, efficient implementation, and extensions to dynamic environments
A multi-resolution path planning algorithm based on the wavelet transform of the environment has been reported previously in the literature. In this paper, we provide a proof of co...
Raghvendra V. Cowlagi, Panagiotis Tsiotras
FCCM
1998
IEEE
169views VLSI» more  FCCM 1998»
15 years 1 months ago
Scalable Network Based FPGA Accelerators for an Automatic Target Recognition Application
Abstract Image processing, specifically Automatic Target Recognition (ATR) in Synthetic Aperture Radar (SAR) imagery, is an application area that can require tremendous processing ...
Ruth Sivilotti, Young Cho, Wen-King Su, Danny Cohe...
ANCS
2007
ACM
15 years 1 months ago
Compiling PCRE to FPGA for accelerating SNORT IDS
Deep Payload Inspection systems like SNORT and BRO utilize regular expression for their rules due to their high expressibility and compactness. The SNORT IDS system uses the PCRE ...
Abhishek Mitra, Walid A. Najjar, Laxmi N. Bhuyan