Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
It has become clear that on-chip storage is an essential component of high-density FPGAs. These arrays were originally intended to implement storage, but recent work has shown tha...
A novel algorithm for object tracking in video pictures, based on image segmentation and pattern matching, as well as its FPGA/ASIC implementation architecture are presented. With ...
K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tet...
Background: This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomic...
Yoginder S. Dandass, Shane C. Burgess, Mark Lawren...
- This paper deals with the efficient realization of a 128-pt FFT/IFFT processor for application in IEEE 802.15.3a standard. The 128-pt FFT/IFFT architecture has been designed by d...