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» Algorithm Transformation for FPGA Implementation
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DAC
2002
ACM
16 years 2 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
FPGA
2000
ACM
109views FPGA» more  FPGA 2000»
15 years 5 months ago
Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays
It has become clear that on-chip storage is an essential component of high-density FPGAs. These arrays were originally intended to implement storage, but recent work has shown tha...
Steven J. E. Wilton
ASPDAC
2006
ACM
173views Hardware» more  ASPDAC 2006»
15 years 5 months ago
Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking
A novel algorithm for object tracking in video pictures, based on image segmentation and pattern matching, as well as its FPGA/ASIC implementation architecture are presented. With ...
K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tet...
BMCBI
2008
214views more  BMCBI 2008»
15 years 1 months ago
Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research
Background: This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomic...
Yoginder S. Dandass, Shane C. Burgess, Mark Lawren...
ISCAS
2005
IEEE
99views Hardware» more  ISCAS 2005»
15 years 7 months ago
On the implementation of 128-pt FFT/IFFT for high-performance WPAN
- This paper deals with the efficient realization of a 128-pt FFT/IFFT processor for application in IEEE 802.15.3a standard. The 128-pt FFT/IFFT architecture has been designed by d...
C. Huggett, K. Maharatna, K. Paul