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» Algorithm Transformation for FPGA Implementation
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DAC
2006
ACM
16 years 2 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
SASP
2009
IEEE
238views Hardware» more  SASP 2009»
15 years 8 months ago
Hardware acceleration of multi-view face detection
—This paper presents a parallelized architecture for hardware acceleration of multi-view face detection. In our architecture, the multi-view face detection system generates rotat...
Junguk Cho, Bridget Benson, Ryan Kastner
106
Voted
FPT
2005
IEEE
181views Hardware» more  FPT 2005»
15 years 7 months ago
Hardware-Accelerated SSH on Self-Reconfigurable Systems
The performance of security applications can be greatly improved by accelerating the cryptographic algorithms in hardware. In this paper, an implementation of the Secure Shell (SS...
Ivan Gonzalez, Francisco J. Gomez-Arribas, Sergio ...
ENTCS
2008
116views more  ENTCS 2008»
15 years 1 months ago
Phil: A Lazy Implementation of a Language for Approximate Filtering of XML Documents
In this paper, we introduce a system, written in Haskell, for filtering information from XML data. Essentially, the system implements a simple declarative language which allows on...
Michele Baggi, Demis Ballis
JMIV
2011
179views more  JMIV 2011»
14 years 8 months ago
3-D Data Denoising and Inpainting with the Low-Redundancy Fast Curvelet Transform
In this paper, we first present a new implementation of the 3-D fast curvelet transform, which is nearly 2.5 less redundant than the Curvelab (wrapping-based) implementation as o...
A. Woiselle, Jean-Luc Starck, Jalal Fadili