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» Algorithm Transformation for FPGA Implementation
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SPAA
2005
ACM
15 years 7 months ago
Using elimination to implement scalable and lock-free FIFO queues
This paper shows for the first time that elimination, a scaling technique formerly applied only to counters and LIFO structures, can be applied to FIFO data structures, specific...
Mark Moir, Daniel Nussbaum, Ori Shalev, Nir Shavit
VLSISP
2011
358views Database» more  VLSISP 2011»
14 years 8 months ago
Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition
Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from superlinear increases in ...
Karthik Nagarajan, Brian Holland, Alan D. George, ...
AHS
2006
IEEE
142views Hardware» more  AHS 2006»
15 years 8 months ago
On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition
To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an onchip pr...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yo...
ICC
2009
IEEE
145views Communications» more  ICC 2009»
15 years 8 months ago
Rapid Prototyping of Clarkson's Lattice Reduction for MIMO Detection
—This paper presents the field-programmable gate array (FPGA) implementation of a variant of the LenstraLenstra-Lov´asz (LLL) lattice reduction (LR) algorithm, known as the Cla...
Luis G. Barbero, David L. Milliner, Tharmalingam R...
FCCM
2009
IEEE
190views VLSI» more  FCCM 2009»
15 years 8 months ago
Optical Flow on the Ambric Massively Parallel Processor Array (MPPA)
The Ambric Massively Parallel Processor Array (MPPA) is a device that contains 336 32-bit RISC processors and is appropriate for embedded systems due to its relatively small physi...
Brad L. Hutchings, Brent E. Nelson, Stephen West, ...