Sciweavers

1108 search results - page 7 / 222
» Algorithm Transformation for FPGA Implementation
Sort
View
FPL
2004
Springer
143views Hardware» more  FPL 2004»
15 years 1 months ago
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation
Abstract. Field-Programmable Gate Arrays (FPGAs) have lately become a popular target for implementing cryptographic block ciphers, as a well-designed FPGA solution can combine some...
Joseph Zambreno, David Nguyen, Alok N. Choudhary
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
15 years 6 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
ISCAS
2005
IEEE
143views Hardware» more  ISCAS 2005»
15 years 3 months ago
Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation
— In this paper, we design and implement an improved hardware-based evolutionary digital filter (EDF) version 2. The EDF is an adaptive digital filter which is controlled by ad...
Masahide Abe, Hiroki Arai, Masayuki Kawamata
SIPS
2008
IEEE
15 years 3 months ago
Efficient image reconstruction using partial 2D Fourier transform
In this paper we present an efficient way of doing image reconstruction using the 2D Discrete Fourier transform (DFT). We exploit the fact that in the frequency domain, informati...
Lanping Deng, Chi-Li Yu, Chaitali Chakrabarti, Jun...
VLSISP
2002
199views more  VLSISP 2002»
14 years 9 months ago
Evaluation of CORDIC Algorithms for FPGA Design
Abstract. This paper presents a study of the suitability for FPGA design of full custom based CORDIC implementations. Since all these methods are based on redundant arithmetic, the...
Javier Valls, Martin Kuhlmann, Keshab K. Parhi