As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
In real sequence labeling tasks, statistics of many higher order features are not sufficient due to the training data sparseness, very few of them are useful. We describe Sparse H...
Parallel architectures are the way of the future, but are notoriously difficult to program. In addition to the low-level constructs they often present (e.g., locks, DMA, and non-...
Despite much research in the area of wireless sensor networks in recent years, the programming of sensor nodes is still time-consuming and tedious. A new paradigm which seems to b...
Christoph Reinke, Nils Hoeller, Jana Neumann, Sven...
Today user-centered information acquisition over collections of complex XML documents is increasingly in demand. To this end, preferences have become an important paradigm enablin...