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ISQED
2009
IEEE
94views Hardware» more  ISQED 2009»
15 years 11 months ago
Simultaneous buffer and interlayer via planning for 3D floorplanning
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong
ICML
2009
IEEE
15 years 11 months ago
Sparse higher order conditional random fields for improved sequence labeling
In real sequence labeling tasks, statistics of many higher order features are not sufficient due to the training data sparseness, very few of them are useful. We describe Sparse H...
Xian Qian, Xiaoqian Jiang, Qi Zhang, Xuanjing Huan...
SAC
2009
ACM
15 years 11 months ago
Celling SHIM: compiling deterministic concurrency to a heterogeneous multicore
Parallel architectures are the way of the future, but are notoriously difficult to program. In addition to the low-level constructs they often present (e.g., locks, DMA, and non-...
Nalini Vasudevan, Stephen A. Edwards
SAC
2009
ACM
15 years 11 months ago
Integrating standardized transaction protocols in service-oriented wireless sensor networks
Despite much research in the area of wireless sensor networks in recent years, the programming of sensor nodes is still time-consuming and tedious. A new paradigm which seems to b...
Christoph Reinke, Nils Hoeller, Jana Neumann, Sven...
SAC
2009
ACM
15 years 11 months ago
Building an efficient preference XML query processor
Today user-centered information acquisition over collections of complex XML documents is increasingly in demand. To this end, preferences have become an important paradigm enablin...
SungRan Cho, Wolf-Tilo Balke
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