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118
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BIBE
2003
IEEE
15 years 10 months ago
An Investigation of Phylogenetic Likelihood Methods
Abstract— We analyze the performance of likelihoodbased approaches used to reconstruct phylogenetic trees. Unlike other techniques such as Neighbor-Joining (NJ) and Maximum Parsi...
Tiffani L. Williams, Bernard M. E. Moret
133
Voted
CGO
2003
IEEE
15 years 10 months ago
Addressing Mode Selection
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...
Erik Eckstein, Bernhard Scholz
CODES
2003
IEEE
15 years 10 months ago
A codesigned on-chip logic minimizer
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
Roman L. Lysecky, Frank Vahid
137
Voted
DATE
2003
IEEE
124views Hardware» more  DATE 2003»
15 years 10 months ago
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration
– Floorplanning large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. This paper presents a global flo...
Wonjoon Choi, Kia Bazargan
131
Voted
DATE
2003
IEEE
99views Hardware» more  DATE 2003»
15 years 10 months ago
Fast Computation of Data Correlation Using BDDs
Data correlation is a well-known problem that causes difficulty in VLSI testing. Based on a correlation metric, an efficient heuristic to select BIST registers has been proposed...
Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maci...
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