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CGO
2005
IEEE
15 years 8 months ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
CODES
2005
IEEE
15 years 8 months ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
ICALT
2005
IEEE
15 years 8 months ago
ActiveTutor
In this paper we present an architecture dedicated to an intelligently assisted educational tool which integrates within a unified framework software rational agents both at the m...
Jean Pierre Fournier
MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
15 years 8 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
VISUALIZATION
2005
IEEE
15 years 8 months ago
Distributed Data Management for Large Volume Visualization
We propose a distributed data management scheme for large data visualization that emphasizes efficient data sharing and access. To minimize data access time and support users wit...
Jinzhu Gao, Jian Huang, C. Ryan Johnson, Scott Atc...
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