Sciweavers

13841 search results - page 2589 / 2769
» Algorithms and Constraint Programming
Sort
View
CGO
2003
IEEE
15 years 8 months ago
Addressing Mode Selection
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...
Erik Eckstein, Bernhard Scholz
123
Voted
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
15 years 8 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
15 years 8 months ago
A Novel Metric for Interconnect Architecture Performance
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Mud...
191
Voted
EH
2003
IEEE
247views Hardware» more  EH 2003»
15 years 8 months ago
Evolvable Building Blocks for Analog Fuzzy Logic Controllers
This work discusses the use of an Evolvable Hardware (EHW) platform in the synthesis of analog electronic circuits for Fuzzy Logic Controllers. A Fuzzy Logic Controller (FLC) is d...
Jorge Luís Machado do Amaral, José F...
135
Voted
INFOCOM
2003
IEEE
15 years 8 months ago
Resource Optimization of Spatial TDMA in Ad Hoc Radio Networks: A Column Generation Approach
—Wireless communications using ad hoc networks are receiving an increasing interest. The most attractive feature of ad hoc networks is the flexibility. The network is set up by ...
Peter Värbrand, Di Yuan, Patrik Björklun...
« Prev « First page 2589 / 2769 Last » Next »