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ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
15 years 10 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 10 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
MMM
2005
Springer
163views Multimedia» more  MMM 2005»
15 years 10 months ago
Parallel Image Matrix Compression for Face Recognition
The canonical face recognition algorithm Eigenface and Fisherface are both based on one dimensional vector representation. However, with the high feature dimensions and the small ...
Dong Xu, Shuicheng Yan, Lei Zhang, Mingjing Li, We...
MINENET
2005
ACM
15 years 10 months ago
Identifying BGP routing table transfers
BGP routing updates collected by monitoring projects such as RouteViews and RIPE have been a vital source to our understanding of the global routing system. The updates logged by ...
Beichuan Zhang, Vamsi Kambhampati, Mohit Lad, Dani...
SAC
2005
ACM
15 years 10 months ago
Adaptive and fault tolerant medical vest for life-critical medical monitoring
In recent years, exciting technological advances have been made in development of flexible electronics. These technologies offer the opportunity to weave computation, communicat...
Roozbeh Jafari, Foad Dabiri, Philip Brisk, Majid S...
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