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» Algorithms for Energy Saving
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ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
15 years 6 months ago
Formal model of data reuse analysis for hierarchical memory organizations
– In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhan...
Ilie I. Luican, Hongwei Zhu, Florin Balasa
ICCAD
2002
IEEE
103views Hardware» more  ICCAD 2002»
15 years 6 months ago
Synthesis of customized loop caches for core-based embedded systems
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
Susan Cotterell, Frank Vahid
MICRO
2006
IEEE
89views Hardware» more  MICRO 2006»
15 years 4 months ago
DMDC: Delayed Memory Dependence Checking through Age-Based Filtering
One of the main challenges of modern processor design is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-o...
Fernando Castro, Luis Piñuel, Daniel Chaver...
MICRO
1999
IEEE
71views Hardware» more  MICRO 1999»
15 years 2 months ago
Selective Cache Ways: On-Demand Cache Resource Allocation
Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip resources to application re...
David H. Albonesi
INFOCOM
2009
IEEE
15 years 4 months ago
Optimal Anycast Technique for Delay-Sensitive Energy-Constrained Asynchronous Sensor Networks
Abstract—In wireless sensor networks, asynchronous sleepwake scheduling protocols can significantly reduce energy consumption without incurring the communication overhead for cl...
Joohwan Kim, Xiaojun Lin, Ness B. Shroff