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PSB
2001
15 years 3 months ago
A Multithreaded Parallel Implementation of a Dynamic Programming Algorithm for Sequence Comparison
This paper discusses the issues involved in implementing a dynamic programming algorithm for biological sequence comparison on a generalpurpose parallel computing platform based o...
W. S. Martins, Juan del Cuvillo, F. J. Useche, Kev...
GECCO
2007
Springer
268views Optimization» more  GECCO 2007»
15 years 8 months ago
Synthesis of analog filters on an evolvable hardware platform using a genetic algorithm
This work presents a novel approach to filter synthesis on a field programmable analog array (FPAA) architecture using a genetic algorithm (GA). First, a Matlab model of the FPA...
Joachim Becker, Stanis Trendelenburg, Fabian Henri...
SWAT
1992
Springer
101views Algorithms» more  SWAT 1992»
15 years 6 months ago
Parallel Algorithms for Priority Queue Operations
This paper presents parallel algorithms for priority queue operations on a p-processor EREWPRAM. The algorithms are based on a new data structure, the Min-path Heap (MH), which is...
Maria Cristina Pinotti, Geppino Pucci
ISCAPDCS
2008
15 years 3 months ago
Implementation of 802.11n on 128-CORE Processor
This article presents the results of a research in applying modern Graphics Processing Units in the field of telecommunications. The most recent Wireless Local Area Network protoc...
A. Akapyev, V. Krylov
TCAD
2008
112views more  TCAD 2008»
15 years 2 months ago
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
Yu Hu, Victor Shih, Rupak Majumdar, Lei He