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ISMVL
1999
IEEE
76views Hardware» more  ISMVL 1999»
15 years 6 months ago
Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates
This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products exp...
Debatosh Debnath, Tsutomu Sasao
SIGCSE
1997
ACM
111views Education» more  SIGCSE 1997»
15 years 6 months ago
Teaching an engineering approach for network computing
Parallelism and concurrency have long been considered as non essential during the cursus of the average programmer. However, thanks to technological advances, new promising forms ...
Eric Dillon, Carlos Gamboa Dos Santos, Jacques Guy...
ECEASST
2008
171views more  ECEASST 2008»
15 years 2 months ago
Type Checking C++ Template Instantiation by Graph Programs
Abstract: Templates are a language feature of C++ and can be used for metaprogramming. The metaprogram is executed by the compiler and outputs source code which is then compiled. T...
Karl Azab, Karl-Heinz Pennemann
160
Voted
ERSA
2009
147views Hardware» more  ERSA 2009»
15 years 5 days ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias
DAC
1999
ACM
16 years 3 months ago
Power Efficient Mediaprocessors: Design Space Exploration
We present a framework for rapidly exploring the design space of low power application-specific programmable processors (ASPP), in particular mediaprocessors. We focus on a catego...
Johnson Kin, Chunho Lee, William H. Mangione-Smith...