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DATE
2002
IEEE
206views Hardware» more  DATE 2002»
15 years 7 months ago
Accurate Area and Delay Estimators for FPGAs
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
Anshuman Nayak, Malay Haldar, Alok N. Choudhary, P...
EH
2002
IEEE
112views Hardware» more  EH 2002»
15 years 7 months ago
Evolving Circuits in Seconds: Experiments with a Stand-Alone Board-Level Evolvable System
The purpose of this paper is twofold: first, to illustrate a stand-alone board-level evolvable system (SABLES) and its performance, and second to illustrate some problems that occ...
Adrian Stoica, Ricardo Salem Zebulum, Michael I. F...
VL
1996
IEEE
130views Visual Languages» more  VL 1996»
15 years 6 months ago
Seeing Systolic Computations in a Video Game World
ToonTalkTM is a general-purpose concurrent programming system in which the source code is animated and the programming environment is like a me. Every abstract computational aspec...
Kenneth M. Kahn
FPL
2006
Springer
161views Hardware» more  FPL 2006»
15 years 6 months ago
Predictive Load Balancing for Interconnected FPGAs
A Field Programmable Gate Array (FPGA), when used as a platform for implementing special-purpose computing architectures, offers the potential for increased functional parallelism...
Jason D. Bakos, Charles L. Cathey, Allen Michalski
ASPDAC
2005
ACM
89views Hardware» more  ASPDAC 2005»
15 years 4 months ago
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
Yan Lin, Fei Li, Lei He