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EGH
2005
Springer
15 years 8 months ago
Fully procedural graphics
The growing application of user-defined programs within graphics processing units (GPUs) has transformed the fixed-function display pipeline into a largely programmable pipeline...
Turner Whitted, James T. Kajiya
WISA
2004
Springer
15 years 7 months ago
Secure and Efficient AES Software Implementation for Smart Cards
In implementing cryptographic algorithms on limited devices such as smart cards, speed and memory optimization had always been a challenge. With the advent of side channel attacks,...
Elena Trichina, Lesya Korkishko
3DPVT
2006
IEEE
229views Visualization» more  3DPVT 2006»
15 years 6 months ago
Fast and Efficient Dense Variational Stereo on GPU
Thanks to their high performance and programmability, the latest graphics cards can now be used for scientific purpose. They are indeed very efficient parallel Single Instruction ...
Julien Mairal, Renaud Keriven, Alexandre Chariot
HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
15 years 6 months ago
The architecture of an optimistic CPU: the WarpEngine
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
John G. Cleary, Murray Pearson, Husam Kinawi
ERSA
2007
142views Hardware» more  ERSA 2007»
15 years 4 months ago
An FPGA Implementation of Reciprocal Sums for SPME
Molecular Dynamics simulations have become an interesting target for acceleration using Field-Programmable Gate Arrays (FPGA). Still to be attempted completely in FPGA hardware is...
Sam Lee, Paul Chow