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ISSS
1995
IEEE
115views Hardware» more  ISSS 1995»
15 years 6 months ago
A system level design methodology for the optimization of heterogeneous multiprocessors
This paper presents a system level design methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. These heterogeneous systems,...
Markus Schwiegershausen, Peter Pirsch
146
Voted
EH
2004
IEEE
163views Hardware» more  EH 2004»
15 years 6 months ago
Towards Evolvable Analog Artificial Neural Networks Controllers
This work deals with the design of analog circuits for Artificial Neural Networks (ANNs) controllers using an Evolvable Hardware (EHW) platform. ANNs are massively parallel system...
José Franco Machado do Amaral, Jorge Lu&iac...
122
Voted
FPGA
2001
ACM
145views FPGA» more  FPGA 2001»
15 years 7 months ago
Simultaneous logic decomposition with technology mapping in FPGA designs
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
Gang Chen, Jason Cong
ISVC
2007
Springer
15 years 8 months ago
Motion Projection for Floating Object Detection
Abstract. Floating mines are a significant threat to the safety of ships in theatres of military or terrorist conflict. Automating mine detection is difficult, due to the unpredict...
Zhaoyi Wei, Dah-Jye Lee, David Jilk, Robert B. Sch...
IEEEPACT
2003
IEEE
15 years 7 months ago
Reactive Multi-Word Synchronization for Multiprocessors
Shared memory multiprocessor systems typically provide a set of hardware primitives in order to support synchronization. Generally, they provide single-word read-modify-write hard...
Phuong Hoai Ha, Philippas Tsigas