224 search results - page 11 / 45 » Algorithms for Solving Boolean Satisfiability in Combination... |
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TACAS
2010
Springer
14 years 9 months ago
2010
Springer
Abstract. We extend the setting of Satisfiability Modulo Theories (SMT) by introducing a theory of costs C, where it is possible to model and reason about resource consumption and ...
ASPDAC
2009
ACM
15 years 6 months ago
2009
ACM
- We proposed a novel Boolean Satisfiability (SAT)-controlled redundancy addition and removal (RAR) algorithm to resolve the performance and quality problems of
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JCSS
2000
14 years 11 months ago
2000
We give the first nontrivial model-independent time-space tradeoffs for satisfiability. Namely, we show that SAT cannot be solved simultaneously in n1+o(1) time and n1space for an...
AICCSA
2006
IEEE
15 years 1 months ago
2006
IEEE
To excite a stuck-open fault in a CMOS combinational circuit, it is only necessary that the output of the gate containing the fault takes on opposite values during the application...
115
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FMCAD
2000
Springer
15 years 3 months ago
2000
Springer
Image computation nds wide application in VLSI CAD, such as state reachability analysis in formal veri cation and synthesis, combinational veri cation, combinational and sequential...