224 search results - page 14 / 45 » Algorithms for Solving Boolean Satisfiability in Combination... |
DAC
1994
ACM
15 years 3 months ago
1994
ACM
Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation. In this paper, we prese...
ACSD
2004
IEEE
15 years 3 months ago
2004
IEEE
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of...
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C3S2E
2010
ACM
15 years 25 days ago
2010
ACM
Propositional satisfiability solving, or SAT, is an important reasoning task arising in numerous applications, such as circuit design, formal verification, planning, scheduling or...
DSD
2004
IEEE
15 years 3 months ago
2004
IEEE
This paper describes principles of a novel two-level multi-output Boolean minimizer FC-Min, namely its Find Coverage phase. The problem of Boolean minimization is approached in a ...
DAC
2001
ACM
16 years 20 days ago
2001
ACM
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...