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» Algorithms for Solving Boolean Satisfiability in Combination...
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ICCAD
1998
IEEE
66views Hardware» more  ICCAD 1998»
15 years 8 months ago
Tight integration of combinational verification methods
Combinational verification is an important piece of most equivalence checking tools. In the recent past, many combinational verification algorithms have appeared in the literature...
Jerry R. Burch, Vigyan Singhal
133
Voted
ICCD
2000
IEEE
120views Hardware» more  ICCD 2000»
15 years 8 months ago
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
This paper presents a verification technique for functional comparison of large combinational circuits using a novel combination of known approaches. The idea is based on a tight...
Viresh Paruthi, Andreas Kuehlmann
128
Voted
FPL
2004
Springer
95views Hardware» more  FPL 2004»
15 years 9 months ago
Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor
Abstract. This paper proposes an architecture that combines a contextswitching virtual configware/software SAT solver with an embedded processor to promote a tighter coupling betwe...
C. J. Tavares, C. Bungardean, G. M. Matos, Jos&eac...
123
Voted
ASPDAC
2004
ACM
145views Hardware» more  ASPDAC 2004»
15 years 9 months ago
Hierarchical random-walk algorithms for power grid analysis
Abstract— This paper presents a power grid analyzer that combines a divide-and-conquer strategy with a random-walk engine. A single-level hierarchical method is first described ...
Haifeng Qian, Sachin S. Sapatnekar
141
Voted
ICCAD
2009
IEEE
159views Hardware» more  ICCAD 2009»
15 years 1 months ago
First steps towards SAT-based formal analog verification
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...