224 search results - page 27 / 45 » Algorithms for Solving Boolean Satisfiability in Combination... |
132
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DAC
2005
ACM
16 years 4 months ago
2005
ACM
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
111
Voted
DATE
2005
IEEE
15 years 9 months ago
2005
IEEE
We discuss fault equivalence and dominance relations for multiple output combinational circuits. The conventional definition for equivalence says that “Two faults are equivalen...
103
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TCAD
2008
15 years 3 months ago
2008
BDDs have proven to be an efficient means to represent and manipulate Boolean formulae [1] and sets [2] due to their compactness and canonicality. In this work, we leverage the eff...
141
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SAT
2005
Springer
15 years 9 months ago
2005
Springer
Much attention has been given in recent years to the problem of finding Minimally Unsatisfiable Subformulas (MUSes) of Boolean formulas. In this paper, we present a new view of the...
134
Voted
GLVLSI
2005
IEEE
15 years 9 months ago
2005
IEEE
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...