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» Algorithms for Solving Boolean Satisfiability in Combination...
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ICCAD
2001
IEEE
124views Hardware» more  ICCAD 2001»
16 years 18 days ago
Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs
Methods based on Boolean satisfiability (SAT) typically use a Conjunctive Normal Form (CNF) representation of the Boolean formula, and exploit the structure of the given problem ...
Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zh...
137
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DATE
2006
IEEE
91views Hardware» more  DATE 2006»
15 years 7 months ago
Efficient incremental clock latency scheduling for large circuits
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
Christoph Albrecht
119
Voted
ATVA
2010
Springer
154views Hardware» more  ATVA 2010»
15 years 4 months ago
Lattice-Valued Binary Decision Diagrams
Abstract. This work introduces a new data structure, called Lattice-Valued Binary Decision Diagrams (or LVBDD for short), for the compact representation and manipulation of functio...
Gilles Geeraerts, Gabriel Kalyon, Tristan Le Gall,...
NECO
2008
129views more  NECO 2008»
15 years 3 months ago
Sparse Coding via Thresholding and Local Competition in Neural Circuits
While evidence indicates that neural systems may be employing sparse approximations to represent sensed stimuli, the mechanisms underlying this ability are not understood. We desc...
Christopher J. Rozell, Don H. Johnson, Richard G. ...
TEC
2002
119views more  TEC 2002»
15 years 3 months ago
Graph-based evolutionary design of arithmetic circuits
Abstract--In this paper, we present an efficient graph-based evolutionary optimization technique called evolutionary graph generation (EGG) and the proposed approach is applied to ...
Dingjun Chen, Takafumi Aoki, Naofumi Homma, Toshik...