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148
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GLVLSI
2008
IEEE
120views VLSI» more  GLVLSI 2008»
15 years 10 months ago
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metaloxide semiconductor (CMOS) technology in future circuit design. H...
Yexin Zheng, Michael S. Hsiao, Chao Huang
100
Voted
DAC
2000
ACM
16 years 4 months ago
The use of carry-save representation in joint module selection and retiming
Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In ...
Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.
121
Voted
DAC
2001
ACM
16 years 4 months ago
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
Jason Cong, Michail Romesis
GECCO
2007
Springer
149views Optimization» more  GECCO 2007»
15 years 10 months ago
Optimal antenna placement using a new multi-objective chc algorithm
Radio network design (RND) is a fundamental problem in cellular networks for telecommunications. In these networks, the terrain must be covered by a set of base stations (or anten...
Antonio J. Nebro, Enrique Alba, Guillermo Molina, ...
163
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JAR
2000
145views more  JAR 2000»
15 years 3 months ago
Logical Cryptanalysis as a SAT Problem
Cryptographic algorithms play a key role in computer security and the formal analysis of their robustness is of utmost importance. Yet, logic and automated reasoning tools are seld...
Fabio Massacci, Laura Marraro