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» Algorithms for the automatic extension of an instruction-set
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JAR
2006
103views more  JAR 2006»
14 years 11 months ago
A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures
We describe an approach to verifying bit-level pipelined machine models using a combination of deductive reasoning and decision procedures. While theorem proving systems such as AC...
Panagiotis Manolios, Sudarshan K. Srinivasan
FPL
2007
Springer
99views Hardware» more  FPL 2007»
15 years 3 months ago
Disjoint Pattern Enumeration for Custom Instructions Identification
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analys...
Pan Yu, Tulika Mitra
DATE
2006
IEEE
118views Hardware» more  DATE 2006»
15 years 5 months ago
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit
Multimedia and communication algorithms from embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floating-poin...
Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Hei...
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
15 years 4 months ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...
GECCO
2009
Springer
166views Optimization» more  GECCO 2009»
15 years 6 months ago
Genetic programming in the wild: evolving unrestricted bytecode
We describe a methodology for evolving Java bytecode, enabling the evolution of extant, unrestricted Java programs, or programs in other languages that compile to Java bytecode. B...
Michael Orlov, Moshe Sipper