Sciweavers

112 search results - page 21 / 23
» Allocation of tasks to specialized processors: A planning ap...
Sort
View
ICPP
2009
IEEE
15 years 4 months ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...
IEEEPACT
2000
IEEE
15 years 2 months ago
Instruction Scheduling for Clustered VLIW DSPs
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...
Rainer Leupers
117
Voted
DAC
2010
ACM
15 years 1 months ago
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
Chenjie Yu, Peter Petrov
APIN
1998
107views more  APIN 1998»
14 years 9 months ago
Multiple Adaptive Agents for Tactical Driving
Abstract. Recent research in automated highway systems has ranged from low-level vision-based controllers to high-level route-guidance software. However, there is currently no syst...
Rahul Sukthankar, Shumeet Baluja, John Hancock
PRICAI
2004
Springer
15 years 3 months ago
Shape Matching for Robot Mapping
We present a novel geometric model for robot mapping based on shape. Shape similarity measure and matching techniques originating from computer vision are specially redesigned for ...
Diedrich Wolter, Longin Jan Latecki