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RTAS
2010
IEEE
15 years 2 months ago
DARTS: Techniques and Tools for Predictably Fast Memory Using Integrated Data Allocation and Real-Time Task Scheduling
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
Sangyeol Kang, Alexander G. Dean
ICDE
2006
IEEE
232views Database» more  ICDE 2006»
16 years 5 months ago
Dual Labeling: Answering Graph Reachability Queries in Constant Time
Graph reachability is fundamental to a wide range of applications, including XML indexing, geographic navigation, Internet routing, ontology queries based on RDF/OWL, etc. Many ap...
Haixun Wang, Hao He, Jeffrey Xu Yu, Jun Yang 0001,...
GLVLSI
2010
IEEE
210views VLSI» more  GLVLSI 2010»
15 years 9 months ago
Overscaling-friendly timing speculation architectures
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
John Sartori, Rakesh Kumar
RTCSA
1998
IEEE
15 years 8 months ago
Wait-Free Snapshots in Real-Time Systems: Algorithms and Performance
Snap-shot mechanisms are used to read a globally consistent set of variable values. Such a mechanism can be used to solve a variety of communication and synchronization problems, ...
Andreas Ermedahl, Hans Hansson, Marina Papatrianta...
ICCAD
2009
IEEE
151views Hardware» more  ICCAD 2009»
15 years 2 months ago
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
Mohit Gupta, Kwangok Jeong, Andrew B. Kahng