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ICCD
2008
IEEE
165views Hardware» more  ICCD 2008»
15 years 8 months ago
Analysis and minimization of practical energy in 45nm subthreshold logic circuits
Abstract— Over the last decade, the design of ultra-lowpower digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contri...
David Bol, Renaud Ambroise, Denis Flandre, Jean-Di...
ICCD
2005
IEEE
165views Hardware» more  ICCD 2005»
15 years 8 months ago
Counter-Based Cache Replacement Algorithms
Recent studies have shown that in highly associative caches, the performance gap between the Least Recently Used (LRU) and the theoretical optimal replacement algorithms is large,...
Mazen Kharbutli, Yan Solihin
ICCAD
2007
IEEE
128views Hardware» more  ICCAD 2007»
15 years 8 months ago
Module assignment for pin-limited designs under the stacked-Vdd paradigm
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
15 years 8 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic
ICCAD
2001
IEEE
144views Hardware» more  ICCAD 2001»
15 years 8 months ago
Faster SAT and Smaller BDDs via Common Function Structure
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponent...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah